Nevertheless, this is a strongly limited resource. If there are many signals in the design that have to be distributed to several blocks, the Long Lines is the ideal routing resource. 16 Direct Connections (total in all four directions) 40 Horizontal Double Lines 40 Vertical Double Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 24 Horizontal Long Lines 24 Vertical Long Lines Figure 53: Hierarchical routing resources for each row/column. The different types of hierarchical resources are illustrated in figure 53, which refers to a Xilinx Virtex-II device. The dedicated resources are used for distribution of e.g. ModelSim is an HDL simulation software from Mentor Graphics.
The hierarchical routing resources are different types of global and local resources used for interconnection between blocks. Single Kernel Simulator technology enables transparent mixing of VHDL and Verilog in one design. An FPGA usually have two different types of routing resources, hierarchical and dedicated. ModelSim simulates behavioral, RTL, and gate-level code - delivering increased design quality and debug productivity with platform-independent compile. Another aspect of which FPGA size to select, is its associated routing resources. However, the size of the FPGA has to be sufficient to house the Ethernet controller together with other, future, functions. Since there is no specific product where this Ethernet controller shall be implemented, it is hard to identify non-functional characteristics that could exclude any FPGA. The memory is needed by FIFOs, which are used when crossing clock domains. 4.5.1 Choosing Target Device There is no need for any hard blocks except memory, which many FPGAs provides. Questa-Intel® FPGA Edition Software replaces ModelSim-Intel® FPGA Edition Software (see product advisory). Feasibility study: Implementation of a gigabit Ethernet controller using an FPGA 4.5 Synthesis This step covers both the selection of device and the synthesis step itself.
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